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M29W800T90N1R Datasheet(PDF) 8 Page - STMicroelectronics |
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M29W800T90N1R Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 33 page  SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write opera- tion on the falling edge at Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18, in Byte-wide organisation DQ15A–1 acts as an additional LSB address line. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A12 and A15. Data Input/Outputs (DQ0-DQ7). T hes e I n- puts/Outputs are used in the Byte-wide and Word- wide organisations. The inpu t is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputsare disabledand when RP is at a Low level. Data Input/Outputs (DQ8-DQ14 and DQ15A–1). These Inputs/Outputs are additionally used in the Word-wide organisation. When BYTEis High DQ8- DQ14 and DQ15A–1 act as the MSB of the Data Input or Output, functioning as described for DQ0- DQ7 above, and DQ8 - DQ15 are ’don’t care’ for command inputs or status outputs. When BYTE is Low, DQ0-DQ14 are high impedance, DQ15A–1 is the Address A–1 input. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects thememory and reducesthe power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Unprotection opera- tion. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to VID level during Block Protection and Unprotection operations. Write Enable (W). This input controls writing to the Command Registerand Addressand Data latches. Byte/Word Organization Select (BYTE) . The BYTE input selects the output configuration for the device: Byte-wide (x8) mode or Word-wide (x16) mode. When BYTE is Low, the Byte-wide mode is selected and the data is read and programmed on DQ0-DQ7. In this mode, DQ8-DQ14 are at high impedance and DQ15A–1 is the LSB address. When BYTE is High, the Word-wide mode is se- lected and the data is read and programmed on DQ0-DQ15. Ready/Busy Output (RB). Ready/Busy is an open-drainoutput and gives the internal state of the P/E.C. of the device. When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When RB is High, the device is ready for any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Standby modes. Reset/Block Temporary Unprotect Input (RP). The RP Input provides hardware reset and pro- tected block(s) temporary unprotection functions. Reset of the memory is acheived by pulling RP to VIL for at least tPLPX. When the reset pulse is given, if the memory is in Read or Standby modes, it will be available for new operations in tPHEL after the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take tPLYH during which the RB signal will be held at VIL. The end of the memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the sector(s) being erased. See Table 14 and Figure 9. Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transi- tion of RP from VIH to VID must slower than tPHPHH. See Table 15 and Figure 9. When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. 8/33 M29W800T, M29W800B |
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