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M48T251VPM Datasheet(PDF) 6 Page - STMicroelectronics |
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M48T251VPM Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 24 page  M48T251Y, M48T251V 6/24 OPERATION MODES Table 2. Operating Modes Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage 1. See Table 12., page 20 for details. READ A READ cycle executes whenever WRITE Enable (WE) is high and Chip Enable (CE) is low (see Fig- ure 5.). The distinct address defined by the 19 ad- dress inputs (A0-A18) specifies which of the 512K bytes of data is to be accessed. Valid data will be accessed by the eight data output drivers within the specified Access Time (tACC) after the last ad- dress input signal is stable, the CE and OE access times, and their respective parameters are satis- fied. When CE tACC and OE tACC are not satisfied, then data access times must be measured from the more recent CE and OE signals, with the limit- ing parameter being tCO (for CE) or tOE (for OE) in- stead of address access. Figure 5. Memory READ Cycle Note: WE is high for a READ cycle. Mode VCC CE OE WE DQ7-DQ0 Power Deselect 4.5V to 5.5V or 3.0V to 3.6V VIH X X High-Z Standby WRITE VIL X VIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High-Z Active Deselect VSO to VPFD (min) (1) X X X High-Z CMOS Standby Deselect ≤ VSO(1) X X X High-Z Battery Back-Up DQ0 - DQ7 ADDRESSES OE CE DATA OUTPUT VALID tOD tODO tOE tRC tCO tACC tCOE tCOE tOH AI04230 |
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