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M48T251V-85PM1TR Datasheet(PDF) 7 Page - STMicroelectronics |
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M48T251V-85PM1TR Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 24 page 7/24 M48T251Y, M48T251V WRITE WRITE Mode (see Figure 6.) occurs whenever CE and WE signals are low (after address inputs are stable). The most recent falling edge of CE and WE will determine when the WRITE cycle begins (the earlier, rising edge of CE or WE determines cycle termination). All address inputs must be kept stable throughout the WRITE cycle. WE must be high (inactive) for a minimum recovery time (tWR) before a subsequent cycle is initiated. The OE control signal should be kept high (inactive) during the WRITE cycles to avoid bus contention. If CE and OE are low (active), WE will disable the out- puts for Output Data WRITE Time (tODW) from its falling edge. Figure 6. Memory WRITE Cycle 1 Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain in a high impedance state during this period. 3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. AI04231 DQ0–DQ7 ADDRESSES WE CE DATA IN STABLE tWR tOEW tDH tDS tWC tODW tWP tAW HIGH IMPEDANCE |
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