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M48T513Y-85CS1 Datasheet(PDF) 10 Page - STMicroelectronics |
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M48T513Y-85CS1 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 23 page M48T513Y, M48T513V 10/23 Table 10. Write Mode AC Characteristics (TA = 0 to 70 °C) Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. Symbol Parameter M48T513Y M48T513V Unit -70 -85 Min Max Min Max tAVAV Write Cycle Time 70 85 ns tAVWL Address Valid to Write Enable Low 0 0 ns tAVEL Address Valid to Chip Enable Low 0 0 ns tWLWH Write Enable Pulse Width 50 60 ns tELEH Chip Enable Low to Chip Enable High 55 65 ns tWHAX Write Enable High to Address Transition 5 5 ns tEHAX Chip Enable High to Address Transition 10 15 ns tDVWH Input Valid to Write Enable High 30 35 ns tDVEH Input Valid to Chip Enable High 30 35 ns tWHDX Write Enable High to Input Transition 5 5 ns tEHDX Chip Enable High to Input Transition 10 15 ns tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 30 ns tAVWH Address Valid to Write Enable High 60 70 ns tAVEH Address Valid to Chip Enable High 60 70 ns tWHQX (1, 2) Write Enable High to Output Transition 5 5 ns If the processor does not reset the timer within the specified period, the M48T513Y/V sets the WDF (Watchdog Flag) and generates a watchdog inter- rupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 7FFF0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a ’0’, the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a ’1’, the watchdog will output a negative pulse on the RST pin for 40 to 200 ms. The Watchdog register and the FT bit will reset to a ’0’ at the end of a Watchdog time-out when the WDS bit is set to a ’1’. The watchdog tim- er can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI) or 2) the microproces- sor can perform a write of the Watchdog Register. The time-out period then starts over. The WDI pin should be tied to VSS if not used. The watchdog will be reset on each transition (edge) seen by the WDI pin. In the order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effec- tively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also dis- able the watchdog function until it is again pro- grammed correctly. A read of the Flags Register will reset the Watchdog Flag (Bit D7; Register 7FFF0h). The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. POWER-ON RESET The M48T513Y/V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for 40 to 200ms after VCC passes VPFD. The RST pin is an open drain output and an appro- priate pull-up resistor to VCC should be chosen to control the rise time. |
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