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M48T513Y-85CS1 Datasheet(PDF) 5 Page - STMicroelectronics |
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M48T513Y-85CS1 Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 23 page  5/23 M48T513Y, M48T513V Table 3. Operating Modes (1) Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details. Mode VCC E G W DQ0-DQ7 Power Deselect 4.5V to 5.5V or 3.0V to 3.6V VIH X X High Z Standby Write VIL XVIL DIN Active Read VIL VIL VIH DOUT Active Read VIL VIH VIH High Z Active Deselect VSO to VPFD (min) (2) X X X High Z CMOS Standby Deselect ≤ VSO (2) X X X High Z Battery Back-up Mode Table 4. AC Measurement Conditions Note that Output Hi-Z is defined as the point where data is no longer driven. Input Rise and Fall Times ≤ 5ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V referred to as BiPORT ™ TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER and Alarm Registers store data in BCD. DATA RETENTION MODE With valid VCC applied, the M48T513Y/V operates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automati- cally deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as ”don’t care”. Note: A power failure during a write cycle may cor- rupt data at the current addressed location, but does not jeopardize the rest of the RAM’s content. At voltages below VPFD (min), the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T513Y/V may re- spond to transient noise spikes on VCC that cross into the deselect window during the time the de- vice is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the M48T513Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max). For a further more detailed review of lifetime calculations, please see Application Note AN1012. TIMEKEEPER REGISTERS The M48T513Y/V offers 16 internal registers which contain TIMEKEEPER, Alarm, Watchdog, Interrupt, Flag, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually Figure 5. AC Testing Load Circuit Note: Excluding open drain output pins. AI01803C CL = 100pF CL includes JIG capacitance 650 Ω DEVICE UNDER TEST 1.75V |
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