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M48Z128CS Datasheet(PDF) 9 Page - STMicroelectronics |
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M48Z128CS Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 17 page 9/17 M48Z128, M48Z128Y POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store en- ergy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic by- pass capacitor value of 0.1 µF (as shown in Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate neg- ative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These nega- tive spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to con- nect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. Supply Voltage Protection AI02169 VCC 0.1 µF DEVICE VCC VSS Table 10. Write Mode AC Characteristics (TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V) Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low after W going low, the outputs remain in the high impedance state. Symbol Parameter M48Z128/M48Z128Y Unit -70 -85 -120 Min Max Min Max Min Max tAVAV Write Cycle Time 70 85 120 ns tAVWL Address Valid to Write Enable Low 0 0 0 ns tAVEL Address Valid to Chip Enable Low 0 0 0 ns tWLWH Write Enable Pulse Width 55 65 85 ns tELEH Chip Enable Low to Chip Enable High 55 75 100 ns tWHAX Write Enable High to Address Transition 5 5 5 ns tEHAX Chip Enable High to Address Transition 15 15 15 ns tDVWH Input Valid to Write Enable High 30 35 45 ns tDVEH Input Valid to Chip Enable High 30 35 45 ns tWHDX Write Enable High to Input Transition 0 0 0 ns tEHDX Chip Enable High to Input Transition 10 10 10 ns tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 30 40 ns tAVWH Address Valid to Write Enable High 65 75 100 ns tAVEH Address Valid to Chip Enable High 65 75 100 ns tWHQX (1, 2) Write Enable High to Output Transition 5 5 5 ns |
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