Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

Note: W = High.

A write is terminated by the earlier rising edge of W

or E. The addresses must be held valid throughout

the cycle. E or W must return high for minimum of

of another read or write cycle. Data-in must be valid

during write cycles to avoid bus contention; al-

though, if the output bus has been activated by a

low on E and G, a low on W will disable the outputs

DATA RETENTION MODE

Should the supply voltage decay, the RAM will

automatically power-fail deselect, write protecting

become high impedance, and all inputs are treated

as ”don’t care.”

If power fail detection occurs during a valid access,

the memory cycle continues to completion. If the

write protection takes place. When Vcc drops be-

internal energy source which preserves data.

The internal coin cell will maintain data in the

an accumulated period of at least 10 years when

and the power supply is switched to external Vcc.

normal RAM operation can resume.

WRITE MODE (cont’d)

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M48Z30, M48Z30Y