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M48T37V-10MH6E Datasheet(PDF) 11 Page - STMicroelectronics |
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M48T37V-10MH6E Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 29 page  11/29 M48T37Y, M48T37V Data Retention Mode With valid VCC applied, the M48T37Y/V operates as a conventional BYTEWIDE™ static RAM. Should the Supply Voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high imped- ance, and all inputs are treated as “Don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's con- tent. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T37Y/V may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. There- fore, decoupling of the power supply lines is rec- ommended. When VCC drops below VSO, the control circuit switches power to the internal battery which pre- serves data and powers the clock. The internal button cell will maintain data in the M48T37Y/V for an accumulated period of at least 7 years at room temperature when VCC is less than VSO. As sys- tem power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Normal RAM operation can resume tREC after VCC reaches VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012. |
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