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M48T59Y-70MH1TR Datasheet(PDF) 10 Page - STMicroelectronics |
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M48T59Y-70MH1TR Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 17 page  DATA RETENTION MODE With valid VCC applied, the M48T58/58Y operates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automat- ically power-fail deselect, write protecting itself when VCC falls within the VPFD(max), VPFD(min) window. All outputs become high impedance, and all inputs are treated as "don’t care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM’s content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T58/58Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. There- fore, decoupling of the power supply lines is rec- ommended. When VCC drops below VSO, the control circuit switches power to the internal battery which pre- serves data and powers the clock. The internal button cell will maintain data in the M48T58/58Y for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tREC (min). E1 should be kept high or E2 low as VCC rises past VPFD(min) to prevent inadvertent write cycles prior to system stabilization. Normal RAM operation can resume tREC after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIME- KEEPER cells in the RAM array are only data registers, and not the actual clock counters, updat- ing the registers can be halted without disturbing the clock itself. Updating is halted when a ’1’ is written to the READ bit, D6 in the Control register (1FF8h). As long as a ’1’ remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated si- multaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a ’0’. Setting the Clock Bit D7 of the Control register (1FF8h) is the WRITE bit. Setting the WRITE bit to a ’1’, like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 10). Resetting the WRITE bit to a ’0’ then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows nor- mal operation to resume. The FT bit and the bits marked as ’0’ in Table 10 must be written to ’0’ to allow for normal TIMEKEEPER and RAM opera- tion. After the WRITE bit is reset, the next clock update will occur within one second. See the Application Note AN923 "TIMEKEEPER rolling into the 21st century" for information on Century Rollover. AI00594B NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION Figure 9. Clock Calibration 10/17 M48T58, M48T58Y |
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