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M50FW002 Datasheet(PDF) 9 Page - STMicroelectronics |
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M50FW002 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 39 page  9/39 M50FW002 Table 4. FWH Bus Read Field Definitions Figure 5. FWH Bus Read Waveforms (1-byte) Clock Cycle Number Clock Cycle Count Field FWH0- FWH3 Memory I/O Description 1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Read cycle. 2 1 IDSEL XXXX I Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. 3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most significant nibble first. 10 1 MSIZE 0X0Xb I Indicates how many bytes will be transferred during multi-byte read operations. The FWH Flash Memory supports 1-byte (0000b), 16-byte (0100b) and 32-byte (0101b) transfers. 11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. 12 1 TAR 1111b (float) O The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. 13-14 2 WSYNC 0101b O The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. 15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least significant nibble. 17+ 5(2n-1) 0 (1-byte) 75 (16-byte) 155 (32-byte) MULTI- BYTE 2 WSYNC + 1 RSYNC + 2 DATA O For each subsequent byte of data repeat cycles 13-17 (2WSYNC + 1RSYNC + 2DATA) 2n-1 times. The FWH Flash Memory supports n = 0000b (1-byte), n = 0100b (16-byte) and n = 0101b (32-byte) reads. Previous +1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. Previous +1 1TAR 1111b (float) N/A The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3. AI03437 CLK FWH4 FWH0-FWH3 Number of clock cycles START IDSEL ADDR MSIZE TAR SYNC DATA TAR 11712322 |
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