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M48T35AY-70PC6TR Datasheet(PDF) 5 Page - STMicroelectronics

Part # M48T35AY-70PC6TR
Description  256 Kbit 32Kb x8 TIMEKEEPER SRAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M48T35AY-70PC6TR Datasheet(HTML) 5 Page - STMicroelectronics

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M48T35AY, M48T35AV
DATA RETENTION MODE
With valid VCC applied, the M48T35AY/35AV op-
erates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD (min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48T35AY/35AV may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35AY/
35AV for an accumulated period of at least 7 years
when VCC is less than VSO. As system power re-
turns and VCC rises above VSO, the battery is dis-
connected, and the power supply is switched to
external VCC. Write protection continues until VCC
reaches VPFD (min) plus tREC (min). E should be
kept high as VCC rises past VPFD (min) to prevent
inadvertent write cycles prior to processor stabili-
zation. Normal RAM operation can resume tREC
after VCC exceeds VPFD (max).
Also, as VCC rises, the battery voltage is checked.
If the voltage is less than approximately 2.5V, an
internal Battery Not OK (BOK) flag will be set. The
BOK flag can be checked after power up. If the
BOK flag is set, the first write attempted will be
blocked. The flag is automatically cleared after the
first write, and normal RAM operation resumes.
Figure 9 illustrates how a BOK check routine could
be structured.
For more information on Battery Storage Life refer
to the Application Note AN1012.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 4. AC Testing Load Circuit
AI02586
CL = 100pF
(or 5pF)
CL includes JIG capacitance
645
DEVICE
UNDER
TEST
1.75V


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