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M50LPW041K1T Datasheet(PDF) 6 Page - STMicroelectronics |
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M50LPW041K1T Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 37 page  M50LPW041 6/37 (RP and INIT) are available to put the memory into a known state. The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection. Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Low Pin Count Registers. A valid Bus Read operation starts when Input Communication Frame, LFRAME, is Low, VIL, as Clock rises and the correct Start cycle is on LAD0-LAD3. On the following clock cycles the Host will send the Cycle Type + Dir, Address and other control bits on LAD0-LAD3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7. Refer to Table 7, LPC Bus Read Field Definitions, and Figure 5, LPC Bus Read Waveforms, for a de- scription of the Field definitions for each clock cy- cle of the transfer. See Table 23, LPC Interface AC Signal Timing Characteristics and Figure 10, LPC Interface AC Signal Timing Waveforms, for details on the timings of the signals. Bus Write. Bus Write operations write to the Command Interface or Low Pin Count Registers. A valid Bus Write operation starts when Input Supply Signal Descriptions The Supply Signals are the same for both interfac- es. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After VCC becomes valid the Command Interface is reset to Read mode. A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both VCC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory. VPP can be left floating. When VPP = VPPH Fast Program (if a Quadruple Byte Program Command is performed) and Fast Erase operations are used. VPP should not be set to VPPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the volt- age measurements. BUS OPERATIONS The two interfaces have similar bus operations but the signals and timings are completely different. The Low Pin Count (LPC) Interface is the usual interface and all of the functionality of the part is available through this interface. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface. Follow the section Low Pin Count (LPC) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface. Low Pin Count (LPC) Bus Operations The Low Pin Count (LPC) Interface consists of four data signals (LAD0-LAD3), one control line (LFRAME) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals Table 4. Signal Names (A/A Mux Interface) IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G Output Enable W Write Enable RC Row/Column Address Select RB Ready/Busy Output RP Interface Reset VCC Supply Voltage VPP Optional Supply Voltage for Fast Program and Fast Erase Operations VSS Ground NC Not Connected Internally |
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