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M-8870-01SMTR Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. M-8870-01SMTR
Description  DTMF Receiver
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Maker  ETC2 [List of Unclassifed Manufacturers]
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Guard time adjustment also allows the designer to tailor system
parameters such as talkoff and noise immunity. Increasing tREC
improves talkoff performance, since it reduces the probability
that tones simulated by speech will maintain signal condition
long enough to be registered. On the other hand, a relatively
short tREC with a long tDO would be appropriate for extremely
noisy environments where fast acquisition time and immunity to
dropouts would be required. Design information for guard time
adjustment is shown in Figure 5.
Power-down and Inhibit Mode ( -02 only)
A logic high applied to pin 6 (PD) will place the device into
standby mode to minimize power consumption. It stops the os-
cillator and the functioning of the filters. On the M-8870-01 mod-
els, this pin is tied to ground (logic low).
Inhibit mode is enabled by a logic high input to pin 5 (INH). It in-
hibits the detection of 1633 Hz. The output code will remain the
same as the previous detected code (see Table 1). On the
M-8870-01 models, this pin is tied to ground (logic low).
Input Configuration
The input arrangement of the M-8870 provides a differential in-
put operational amplifier as well as a bias source (VREF) to bias
the inputs at mid-rail. Provision is made for connection of a feed-
back resistor to the op-amp output (GS) for gain adjustment.
In a single-ended configuration, the input pins are connected as
shown in Figure 4 with the op-amp connected for unity gain and
VREF biasing the input at 1/2VDD. Figure 6 shows the differential
configuration, which permits gain adjustment with the feedback
resistor R5.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a stan-
dard 3.579545 MHz television color burst crystal. The crystal
can be connected to a single M-8870 as shown in Figure 4, or to
a series of M-8870s. As illustrated in Figure 7, a single crystal
can be used to connect a series of M-8870s by coupling the os-
cillator output of each M-8870 through a 30 pF capacitor to the
oscillator input of the next M-8870.
Page 3
M-8870
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288
40-406-00011, Rev. E
E-mail: info@teltone.com Internet: www.teltone.com
Figure 5 Guard Time Adjustment
Pin
Name
Description
1
IN+
Non-inverting input
Connections to the front-end differential amplifier.
2
IN-
Inverting input
3GS
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
4VREF
Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
5
INH*
Inhibits detection of tones representing keys A, B, C, and D.
6
PD*
Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
7
OSC1
Clock input
3.579545 MHz crystal connected between these pins completes the internal oscillator.
8
OSC2
Clock output
9VSS
Negative power supply (normally connected to 0 V).
10
OE
Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
11 - 14
Q1, Q2,
Q3, Q4
Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received (see
Table 5).
15
StD
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is up-
dated. Returns to logic low when the voltage on St/GT falls below VTSt.
16
ESt
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (sig-
nal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17
St/GT
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register
the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair.
The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St.
(See Figure 7).
18
VDD
Positive power supply. (Normally connected to +5V.)
* -02 only. Connect to VSS for -01 version
Table 1 Pin Functions




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