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TLV571 Datasheet(PDF) 3 Page - Texas Instruments |
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TLV571 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description analog-to-digital SAR converter _ + Charge Redistribution DAC SAR Register REFM ADC Code Control Logic Ain Figure 1 The TLV571 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC. The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated. sampling frequency, fs The TLV571 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling frequency achievable with a given CLK frequency is: fs(max) = (1/16) fCLK The TLV571 is software configurable. The first two MSB bits, D(7,6) are used to address which register to set. The remaining six bits are used as control data bits. There are two control registers, CR0 and CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A description of the control registers is shown in Figure 2. |
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