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SN74LV573ATDGVR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV573ATDGVR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) OE To Seven Other Channels 1 11 2 19 LE 1D C1 1D 1Q SN74LV573AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES574C – JUNE 2004 – REVISED AUGUST 2005 A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (EACH LATCH) INPUTS OUTPUTS Q OE LE D L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSTIVE LOGIC) 2 |
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