6

S71NS-N MCP Products

S71NS-N_00_A7 March 26, 2008

Data

Sheet

(Adv an ce

Inf o r m a t io n)

3.

MCP Block Diagram

Figure 3.1 MCP Block Diagram

Note

The CLK and WAIT signals on the pSRAM are not present on the pSRAM Type 2; therefore, for those MCP's, those signals will only be

connected to the NS flash, but not to the pSRAM. Also, on this pSRAM, the CRE signal will not be present at all.

4.

Connection Diagrams/Physical Dimensions

This section contains the I/O designations and package specifications for the S71NS-N.

4.1

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The

package and/or data integrity may be compromised if the package body is exposed to temperatures above

150°C for prolonged periods of time.

F-RST#

RST#

F-ACC

ACC

F-WP#

WP#

RDY

RDY/ WAIT

F-CE#

CE#

OE#

OE#

WE#

WE#

AD15-AD0

AD15-AD0

AVD#

AVD#

CLK

CLK

Amax-A16

Amax-A16

CRE

UB#

LB#

WAIT

R-CE#

CE#

OE#

WE#

AD15-AD0

AVD#

CLK

Amax-A16

NS

pSRAM

R-CRE

R-UB#

R-LB #