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TPS77333DGK Datasheet(PDF) 4 Page - Texas Instruments |
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TPS77333DGK Datasheet(HTML) 4 Page - Texas Instruments |
4 / 26 page TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION TPS773XX FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) RESET 2 O Reset output EN 3 I Enable input GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage TPS774XX FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) PG 2 O Power good EN 3 I Enable input GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage TPS773xx RESET timing diagram † Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VI Vres† t t t VO Threshold Voltage RESET Output 220 ms Delay 220 ms Delay Output Undefined Output Undefined VIT +‡ VIT –‡ VIT –‡ VIT +‡ ‡ VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. Vres† |
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