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A6278ELW-T Datasheet(PDF) 7 Page - Allegro MicroSystems |
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A6278ELW-T Datasheet(HTML) 7 Page - Allegro MicroSystems |
7 / 18 page Serial-Input, Constant-Current Latched LED Drivers with Open LED Detection A6278 and A6279 7 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Normal Mode Serial data present at the SERIAL DATA IN input is transferred to the shift register on the logic 0-to-logic 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the register shifts data towards the SERIAL DATA OUT pin. The serial data must appear at the input prior to the rising edge of the CLOCK input waveform. Data present in any register is transferred to the respective latch when the LATCH ENABLE input is high (serial-to-parallel con- version). The latches continue to accept new data as long as the LATCH ENABLE input is held high. Applications where the latches are bypassed (LATCH ENABLE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, the output sink drivers are disabled (OFF). The data stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input active (low), the outputs are controlled by the state of their respective latches. LED Open Circuit Detection (Test) Mode The LED Open Circuit Detection (OCD) mode, or Test mode, is entered by clocking in the LED OCD mode initialization sequence on the OUTPUT ENABLE (OE) and LATCH ENABLE (LE) pins. In Normal mode, the OE and LE pins do not change states while the CLOCK signal is cycling. The initialization sequence is shown in panel A of the LED OCD timing require- ments diagram on page 7. Note: Each step event during mode sequencing happens on the leading edge of the CLOCK signal. Five step events (CLOCK pulses) are required to enter OCD mode and five step events are required to return to Normal mode. A pattern, such as all highs, should first be loaded into the reg- isters and latched leaving LE low. The device is then sequenced into LED OCD mode. It should be noted that data is still being sent through the shift registers while entering the LED OCD mode. However, this data is not latched when the LE pin goes high and sees a CLOCK pulse during the initialization sequence. Open circuit detection does not take place until the sequence in Panel B on page 7 is performed. During this sequence, the OE pin must be held low for a minimum of 2 μs (tW(OE1)) to ensure proper settling of the output currents and be given a minimum of three CLOCK pulses. During the period that the OE pin is low (active), OCD testing begins. The VCE voltage on each of the output pins is compared to the Open LED Detection Theshold, VCE(OCD). If the VCE of an enabled output is lower than VCE(OCD), an error bit value of 0 is set in the corresponding shift register. A value of 1 will be set if no error is detected. If a particular output is not enabled, a 0 will be set. The error codes are summarized in the following table: After the testing process, setting the OE pin high causes the shift registers to latch the error code data where it can then be clocked out of the SERIAL DATA OUT pin. The OCD latching sequence (OE low, 3 CLOCK pulses, OE high as shown in panel B of the LED OCD timing diagram) can then be repeated if necessary to look for intermittent contact problems. The state of the outputs can be programmed with new data at any time while in LED OCD mode (the same as in Normal mode). This allows specific patterns to be tested for open circuits. The pattern that is latched will then be tested during the OCD latching sequence and the resulting bit values can be clocked out of the SERIAL DATA OUT pin. Note: LED Open Circuit Detection will not work properly if the current is being externally limited by resistors to within the set current limit for the device. To return to Normal mode, perform the clocking sequence shown in panel C of the timing diagram on the OE and LE pins. Functional Description Output State Test Condition Error Code Meaning Output State Test Condition Error Code Meaning OFF N/A 0 N/A ON VCE < VCE(OCD) 0 Open/TSD VCE ≥ VCE(OCD) 1 Normal |
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