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ADS5560IRGZT Datasheet(PDF) 5 Page - Texas Instruments

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Part # ADS5560IRGZT
Description  16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5560IRGZT Datasheet(HTML) 5 Page - Texas Instruments

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ELECTRICAL CHARACTERISTICS (Continued)
ADS5560
ADS5562
www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008
Typical values are at 25
°C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, sine wave input clock, 1.5 V
PP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, 0 dB fine
gain
(1).
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling
rate = Max Rated, default fine gain (1dB), unless otherwise noted.
ADS5562
ADS5560
Fs = 80 MSPS
Fs = 40 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
AC CHARACTERISTICS
FIN = 3 MHz
84
84.3
FIN = 10 MHz
79
83.8
80
84
LVDS
dBFS
interface
FIN = 25 MHz
83.2
82.5
SNR
FIN = 30 MHz
82.8
81.8
Signal to noise
FIN = 3 MHz
81.7
83.5
ratio
FIN = 10 MHz
77
81.4
78
83.1
CMOS
dBFS
interface
FIN = 25 MHz
80.7
81.8
FIN = 30 MHz
80.4
81.6
RMS output noise
Inputs tied to common-mode
1.42
1.42
LSB
FIN = 3 MHz
80.5
83.2
FIN = 10 MHz
75
80.5
76
83
LVDS
dBFS
interface
FIN = 25 MHz
79.5
79
SINAD
FIN = 30 MHz
79
77
Signal to noise and
FIN = 3 MHz
80.5
82
distortion ratio
FIN = 10 MHz
73.5
80.2
75
81.4
CMOS
dBFS
interface
FIN = 25 MHz
79.3
79.3
FIN = 30 MHz
77.9
78
ENOB
LVDS
Effective number
FIN = 10 MHz
12.2
13.1
12.4
13.5
bits
interface
of bits
FIN = 3 MHz
85
90
SFDR
FIN = 10 MHz
77
85
78
88
Spurious free
dBc
FIN = 25 MHz
83
83
dynamic range
FIN = 30 MHz
80
79
FIN = 3 MHz
90
94
FIN = 10 MHz
77
89
78
92
HD2
dBc
Second harmonic
FIN = 25 MHz
88
90
FIN = 30 MHz
88
88
(1)
Note that after reset, the device is initialized to 1 dB fine gain setting. For SFDR and SNR performance across fine gains, see Typical
Characteristics section.
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS5560 ADS5562


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