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DS18B20 Datasheet(PDF) 15 Page - Dallas Semiconductor |
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DS18B20 Datasheet(HTML) 15 Page - Dallas Semiconductor |
15 / 22 page DS18B20 15 of 22 1-WIRE SIGNALING The DS18B20 uses a strict 1-Wire communication protocol to ensure data integrity. Several signal types are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. The bus master initiates all these signals, with the exception of the presence pulse. INITIALIZATION PROCEDURE—RESET AND PRESENCE PULSES All communication with the DS18B20 begins with an initialization sequence that consists of a reset pulse from the master followed by a presence pulse from the DS18B20. This is illustrated in Figure 13. When the DS18B20 sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus and ready to operate. During the initialization sequence the bus master transmits (TX) the reset pulse by pulling the 1-Wire bus low for a minimum of 480 μs. The bus master then releases the bus and goes into receive mode (R X). When the bus is released, the 5k Ω pullup resistor pulls the 1-Wire bus high. When the DS18B20 detects this rising edge, it waits 15 μs to 60μs and then transmits a presence pulse by pulling the 1-Wire bus low for 60 μs to 240μs. Figure 13. Initialization Timing READ/WRITE TIME SLOTS The bus master writes data to the DS18B20 during write time slots and reads data from the DS18B20 during read time slots. One bit of data is transmitted over the 1-Wire bus per time slot. WRITE TIME SLOTS There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master uses a Write 1 time slot to write a logic 1 to the DS18B20 and a Write 0 time slot to write a logic 0 to the DS18B20. All write time slots must be a minimum of 60 μs in duration with a minimum of a 1μs recovery time between individual write slots. Both types of write time slots are initiated by the master pulling the 1-Wire bus low (see Figure 14). To generate a Write 1 time slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wire bus within 15 μs. When the bus is released, the 5kΩ pullup resistor will pull the bus high. To generate a Write 0 time slot, after pulling the 1-Wire bus low, the bus master must continue to hold the bus low for the duration of the time slot (at least 60 μs). LINE TYPE LEGEND Bus master pulling low DS18B20 pulling low Resistor pullup VPU GND 1-WIRE BUS 480 μs minimum 480 μs minimum DS18B20 TX presence pulse 60-240 μs MASTER TX RESET PULSE MASTER RX DS18B20 waits 15-60 μs |
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