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MC74VHCT257ADR2 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74VHCT257ADR2 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2004 September, 2004 − Rev. 2 1 Publication Order Number: MC74VHCT257A/D MC74VHCT257A Quad 2−Channel Multiplexer with 3−State Outputs The MC74VHCT257A is an advanced high speed CMOS quad 2−channel multiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. It consists of four 2−input digital multiplexers with common select (S) and enable (OE) inputs. When (OE) is held High, selection of data is inhibited and all the outputs go Low. The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V because it has full 5 V CMOS level output swings. The VHCT257A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage—input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems. • High Speed: t PD = 4.1 ns (Typ) at VCC = 5.0 V • Low Power Dissipation: I CC = 4.0 mA (Max) at TA = 25°C • TTL−Compatible Inputs: V IL = 0.8 V; VIH = 2.0 V • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Designed for 2.0 V to 5.5 V Operating Range • Low Noise: V OLP = 0.8 V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300 mA • ESD Performance: HBM > 2000 V; Machine Model > 200 V Figure 1. Pin Assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 S Y0 B0 A0 Y1 B1 A1 GND Y3 B3 A3 OE VCC B2 A2 Y2 SO−16 SO−16 D SUFFIX CASE 751B MARKING DIAGRAMS 1 8 9 16 1 8 16 9 VHCT257A AWLYWW VHCT257A ALYW TSSOP−16 DT SUFFIX CASE 948F ORDERING INFORMATION EIAJ SO−16 M SUFFIX CASE 966 VHCT257A ALYW A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week 16 9 1 8 Device Package Shipping† MC74VHCT257AD SO−16 48 Units/Rail MC74VHCT257ADT TSSOP−16 96 Units/Rail MC74VHCT257AM EIAJSO−16 50 Units/Rail MC74VHCT257ADR2 2500 Tape & Reel MC74VHCT257ADTR2 TSSOP−16 2500 Tape & Reel MC74VHCT257AMEL EIAJSO−16 2000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com |
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