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MT16VDDF12864H Datasheet(PDF) 10 Page - Micron Technology |
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MT16VDDF12864H Datasheet(HTML) 10 Page - Micron Technology |
10 / 31 page 512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 10 ©2003 Micron Technology, Inc. NOTE: 1. For a burst length of two, A1-Ai select the two-data-ele- ment block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the four-data- element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eight-data- element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (512MB); i = 9,11 (1GB) Figure 6: CAS Latency Diagram Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A12 each set to zero, and bits A0–A6 set to the desired val- ues. A DLL reset is initiated by issuing a MODE REGIS- TER SET command with bits A7 and A9–A12 each set to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operat- ing mode. All other combinations of values for A7–A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and out- put drive strength. These functions are controlled via the bits shown in Figure 7, Extended Mode Register Definition Diagram, on page 11. The extended mode register is programmed via the LOAD MODE REGIS- TER command to the mode register (with BA0 = 1 and Table 6: Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED 2 A0 00-1 0-1 11-0 1-0 4 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Table 7: CAS Latency (CL) Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 -335 75 £ f £ 133 75 £ f £ 167 -262 75 £ f £ 133 75 £ f £ 133 -26A 75 £ f £ 133 75 £ f £ 133 -265 75 £ f £ 100 75 £ f £ 133 -202 75 £ f £ 100 75 £ f £ 125 CK CK# COMMAND DQ DQS CL = 2 READ NOP NOP NOP READ NOP NOP NOP Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ CK CK# COMMAND DQ DQS CL = 2.5 T0 T1 T2 T2n T3 T3n T0 T1 T2 T2n T3 T3n DON T CARE TRANSITIONING DATA |
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