512MB, 1GB (x64)

200-PIN DDR SODIMM

09005aef80a646bc

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN

9

©2003 Micron Technology, Inc.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Figure 5, Mode Register Definition

Diagram. The burst length determines the maximum

number of column locations that can be accessed for a

given READ or WRITE command. Burst lengths of 2, 4,

or 8 locations are available for both the sequential and

the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1–Ai when the burst length is set to two,

by A2–Ai when the burst length is set to four and by

A3–Ai when the burst length is set to eight (where Ai is

the most significant column address bit for a given

configuration. See Note 5 of Table 6, Burst Definition

Table, on page 10, for Ai values). The remaining (least

significant) address bit(s) is (are) used to select the

starting location within the block. The programmed

burst length applies to both read and write bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 6, Burst

Definition Table, on page 10.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS

Latency Diagram, on page 10.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. The CAS

Latency Table indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Figure 5: Mode Register Definition

Diagram

Burst Length

CAS Latency BT

0*

A9

A7 A6 A5 A4 A3

A8

A2 A1 A0

Mode Register (Mx)

Address Bus

9

7

65

4

3

8

2

1

0

Operating Mode

A10

A12 A11

BA1 BA0

10

11

12

13

0*

14

* M14 and M13 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M3 = 0

Reserved

2

4

8

Reserved

Reserved

Reserved

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

0

1

-

0

0

-

0

0

-

0

0

-

0

0

-

0

0

-

Valid

Valid

-

0

1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Reserved

2

Reserved

Reserved

Reserved

2.5

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

M1

0

0

1

1

0

0

1

1

M2

0

0

0

0

1

1

1

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

0

1

1

0

0

1

1

M6

0

0

0

0

1

1

1

1

M6-M0

M8 M7

M9

M10

M12 M11

0

0

-

M13