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M74HC597 Datasheet(PDF) 1 Page - STMicroelectronics |
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M74HC597 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 13 page  M54HC597 M74HC597 October 1992 8 BIT LATCH/SHIFT REGISTER B1R (Plastic Package) ORDER CODES : M54HC597F1R M74HC597M1R M74HC597B1R M74HC597C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection . HIGH SPEED fMAX = 60 MHz (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS597 The M54/74HC597 is a high speed CMOS 8-BIT LATCH/SHIFT REGISTER fabricated in silicon gate C 2MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. This devices comes in a 16-pin package and consist of an 8-bit storage latch feeding a parallel-in, serial- out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. All inputs are equipped with protection circuits against static discharge and transient voltage ex- cess. DESCRIPTION 1/13 |
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