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MPR084 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MPR084 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 39 page MPR084 Sensors 6 Freescale Semiconductor Preliminary 2.3.2 Start and Stop Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Figure 6. Start and Stop Conditions 2.3.3 Bit Transfer One data bit is transferred during each clock pulse (Figure 7). The data on SDA must remain stable while SCL is high. Figure 7. Bit Transfer 2.3.4 Acknowledge The acknowledge bit is a clocked 9th bit (Figure 8) which the recipient uses to handshake receipt of each byte of data. Thus each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MPR084, the MPR084 generates the acknowledge bit because the MPR084 is the recipient. When the MPR084 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. Figure 8. Acknowledge DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED SDA SCL START CONDITION SDA SCL STOP CONDITION P S START CONDITION SDA BY TRANSMITTER S 12 8 9 CLOCK PULSE FOR ACKNOWLEDGEMENT SDA BY RECEIVER SCL |
Similar Part No. - MPR084 |
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Similar Description - MPR084 |
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