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AT91SAM7S128-AU-001 Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT91SAM7S128-AU-001 Datasheet(HTML) 1 Page - ATMEL Corporation |
1 / 42 page Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded*ICE™ In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 256 kbytes, organized in 1024 Pages of 256 Bytes (AT91SAM7S256) – 128 kbytes, organized in 512 Pages of 256 Bytes (AT91SAM7S128) – 64 kbytes, organized in 512 Pages of 128 Bytes (AT91SAM7S64) – 32 kbytes, organized in 256 Pages of 128 Bytes (AT91SAM7S321/32) – Single Cycle Access at Up to 30 MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms – 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production • Internal High-speed SRAM, Single-cycle Access at Maximum Speed – 64 kbytes (AT91SAM7S256) – 32 kbytes (AT91SAM7S128) – 16 kbytes (AT91SAM7S64) – 8 kbytes (AT91SAM7S321/32) • Memory Controller (MC) – Embedded Flash Controller, Abort Status and Misalignment Detection • Reset Controller (RSTC) – Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector – Provides External Reset Signal Shaping and Reset Source Status • Clock Generator (CKGR) – Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL • Power Management Controller (PMC) – Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode – Three Programmable External Clock Signals • Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two (AT91SAM7S256/128/64/321) or One (AT91SAM7S32) External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected • Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention • Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter • Windowed Watchdog (WDT) – 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode • Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator AT91 ARM® Thumb®-based Microcontrollers AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321 AT91SAM7S32 Summary 6175BS–ATARM–04-Nov-05 |
Similar Part No. - AT91SAM7S128-AU-001 |
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Similar Description - AT91SAM7S128-AU-001 |
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