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S29NS016J0LBFW000 Datasheet(PDF) 3 Page - SPANSION |
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S29NS016J0LBFW000 Datasheet(HTML) 3 Page - SPANSION |
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3 / 73 page  Publication Number S29NS-J_00 Revision A Amendment 11 Issue Date February 7, 2007 Features Single 1.8 volt read, program and erase (1.7 to 1.95 V) Multiplexed Data and Address for reduced I/O count – A15–A0 multiplexed as DQ15–DQ0 – Addresses are latched by AVD# control input when CE# low Simultaneous Read/Write operation – Data can be continuously read from one bank while executing erase/program functions in other bank – Zero latency between read and write operations Read access times at 54 MHz (CL=30 pF) – Burst access times of 11/13.5 ns at industrial temperature range – Asynchronous random access times of 65/70 ns – Synchronous random access times of 71/87.5 ns Burst Modes – Continuous linear burst – 8/16/32 word linear burst with wrap around – 8/16/32 word linear burst without wrap around Power dissipation (typical values, 8 bits switching, CL = 30 pF) – Burst Mode Read: 25 mA – Simultaneous Operation: 40 mA – Program/Erase: 15 mA – Standby mode: 9 µA Sector Architecture – Four 8 Kword sectors – Two hundred fifty-five (S29NS128J), one hundred twenty-seven (S29NS064J),sixty-three (S29NS032J), or thirty-one (S29NS016J) 32 Kword sectors – Four banks (see next page for sector count and size) Sector Protection – Software command sector locking – WP# protects the two highest sectors – All sectors locked when Acc = VIL Handshaking feature – Provides host system with minimum possible latency by monitoring RDY Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards – Backwards compatible with Am29F and Am29LV families Manufactured on 110 nm process technology Embedded Algorithms – Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors – Embedded Program algorithm automatically writes and verifies data at specified addresses Data# Polling – Provides a software method of detecting program and erase operation completion Erase Suspend/Resume – Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Hardware reset input (RESET#) – Hardware method to reset the device for reading array data CMOS compatible inputs and outputs Package – 48-ball Very Thin FBGA (S29NS128J) – 44-ball Very Thin FBGA (S29NS064J, S29NS032J, S29NS016J) Cycling Endurance: 1 million cycles per sector typical Data Retention: 20 years typical General Description The S29NS128J, S29NS064J, S29NS032J and S29NS016J are 128 Mbit, 64 Mbit, 32 Mbit and 16 Mbit 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 8,388,608, 4,194,304, 2,097,152 and 1,048,576. words of 16 bits each. These devices use a single VCC of 1.7 to 1.95 V to read, program, and erase the memory array. A 12.0- volt Acc may be used for faster program performance if desired. These devices can also be programmed in standard EPROM programmers. The devices are offered at the following speeds: S29NS-J 128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit), 32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit), 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories Data Sheet Clock Speed Burst Access (ns) Synch. Initial Access (ns) Asynchronous Initial Access (ns) Output Loading 54 MHz 13.5 87.5 70 30 pF |
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