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M58LW064BZA Datasheet(PDF) 11 Page - STMicroelectronics |
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M58LW064BZA Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 53 page  11/53 M58LW064A, M58LW064B Burst Clock (K). The Burst Clock K is used only in burst mode. It is the fundamental synchronous signal that allows internal latching of the address from the address bus, together with Latch Enable L; increment of the internal address counter in as- sociation with Burst Address Advance B; and to in- dicate valid data on the external data bus. All these operations are synchronously controlled on the valid edge of the Burst Clock K, which can be selected to be the rising or falling edge depending on the definition in the Burst Configuration Regis- ter. For Asynchronous Read or Write, the Burst Clock K input level is Don’t Care. For Synchronous Burst Read the address is latched on the first valid clock edge when Latch Enable L is at VIL, or the rising edge of Latch Enable L, whichever occurs first. Burst Address Advance (B). Burst Address Ad- vance B enables increment of the internal address counter when it falls to VIL during Synchronous Burst Read. It is sampled on the last valid edge of the Burst Clock K at the expiry of the X-latency time. If sampled at VIL, new data will be output on the next Burst Clock K valid edge (or second next depending on the definition in the Burst Configura- tion Register). If it is at VIH when sampled, the pre- vious data remains on the Data Outputs. The Burst Address Advance B may be tied to VIL. Ready (R). The Valid Data Ready R is an output signal used during Synchronous Burst Read. It in- dicates, at the valid clock edge (or one cycle be- fore depending on the definition in the Burst Configuration Register), if valid data is ready on the Data Outputs. New Data Outputs are valid if Valid Data Ready R is at VIH, the previous Data Outputs remain active if Valid Data Ready R is at VIL. In all operations except Burst Read, Valid Data Ready R is at VIH. It may be tied to other compo- nents with the same Valid Data Ready R signal to create a unique system Ready signal. The Valid Data Ready R output has an internal pull-up resis- tor of around 1 M Ω powered from VDDQ, designers should use an external pull-up resistor of the cor- rect value to meet the external timing require- ments for R going to VIH. Word Organisation (WORD). The Word Organi- sation WORD input is present only on the M58LW064B and selects x16 or x32 organisation. The WORD input selects the data width as Word wide (x16) or Double-Word wide (x32). When WORD is at VIL, Word-wide x16 width is selected and data is read and programmed on DQ0-DQ15, DQ16-DQ31 are at high impedance and A1 is the LSB address. When WORD is at VIH, the Double- Word wide x32 width is selected and the data is read and programmed on DQ0-DQ31, and A2 is the LSB address. Ready/Busy (RB). Ready/Busy RB is an open- drain output and gives the internal state of the P/ E.C. When Ready/Busy RB is at VIL the device is busy with a Program or Erase operation and it will not accept any additional program or erase in- structions except for the Program or Erase Sus- pend instructions. When a Program or Erase Suspend is given the RB signal rises to VIH, after a latency time, to indicate that the Command Inter- face is ready for a new instruction. When RB is at VIH, the device is ready for any Read, Program or Erase operation. Ready/Busy RB is also at VIH when the memory is in Erase/Program Suspend or Standby modes. Program/Erase Enable (VPP). Program/Erase Enable VPP automatically protects all blocks from programming or erasure when at VIL. Supply Voltage (VDD). The Supply Voltage VDD is the main power supply for all operations (Read, Program and Erase). Input/Output Supply Voltage (VDDQ). The In- put/Output Supply Voltage VDDQ is the Input and Output buffer power supply for all operations (Read, Program and Erase). Ground (VSS). Ground VSS is the reference for all the voltage measurements. |
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