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M58MR032C120ZC6T Datasheet(PDF) 4 Page - STMicroelectronics |
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M58MR032C120ZC6T Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 52 page  M58MR032C, M58MR032D 4/52 The architecture includes a 128 bits Protection register that is divided into two 64-bits segments. In the first one is written a unique device number, while the second one is programmable by the us- er. The user programmable segment can be per- manently protected programming the bit 1 of the Protection Lock Register (see protection register and Security Block). The parameter block (# 0) is a security block. It can be permanently protected by the user programming the bit 2 of the Protection Lock Register. Block protection against Program or Erase pro- vides additional data security. All blocks are pro- tected and unlocked at Power-up. Instructions are provided to protect or un-protect any block in the application. A second register locks the protection status while WP is low (see Block Locking descrip- tion). Table 3. Bank Size and Sectorization Bank Size Parameter Blocks Main Blocks Bank A 8 Mbit 8 blocks of 4 KWord 15 blocks of 32 KWord Bank B 24 Mbit - 48 blocks of 32 KWord Figure 3. Memory Map AI90069 512 Kbit or 32 KWord 000000h 007FFFh 512 Kbit or 32 KWord 1F0000h 1F7FFFh Top Boot Block Address lines A20-A0 512 Kbit or 32 KWord 178000h 17FFFFh Total of 48 Main Blocks 512 Kbit or 32 KWord 180000h 187FFFh 64 Kbit or 4 KWord 1FF000h 1FFFFFh 64 Kbit or 4 KWord 1F8000h 1F8FFFh Total of 15 Main Blocks Total of 8 Parameter Blocks Bank B Bank A 64 Kbit or 4 KWord 000000h 000FFFh 512 Kbit or 32 KWord 078000h 07FFFFh Bottom Boot Block Address lines A20-A0 64 Kbit or 4 KWord 007000h 007FFFh Total of 8 Parameter Blocks 512 Kbit or 32 KWord 008000h 00FFFFh 512 Kbit or 32 KWord 1F8000h 1FFFFFh 512 Kbit or 32 KWord 080000h 087FFFh Total of 15 Main Blocks Total of 48 Main Blocks Bank B Bank A |
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