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M58MR064C120ZC6T Datasheet(PDF) 4 Page - STMicroelectronics |
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M58MR064C120ZC6T Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 52 page  M58MR064C, M58MR064D 4/52 The architecture includes a 128 bits Protection register that is divided into two 64-bits segments. In the first one is written a unique device number, while the second one is programmable by the us- er. The user programmable segment can be per- manently protected programming the bit 1 of the Protection Lock Register (see protection register and Security Block). The parameter block (# 0) is a security block. It can be permanently protected by the user programming the bit 2 of the Protection Lock Register. Block protection against Program or Erase pro- vides additional data security. All blocks are pro- tected and unlocked at Power-up. Instructions are provided to protect or un-protect any block in the application. A second register locks the protection status while WP is low (see Block Locking descrip- tion). Table3. BankSizeand Sectorization Bank Size Parameter Blocks Main Blocks Bank A 16 Mbit 8 blocks of 4 KWord 31 blocks of 32 KWord Bank B 48 Mbit - 96 blocks of 32 KWord Figure 3. Memory Map AI90089 512 Kbit or 32 KWord 000000h 007FFFh 512 Kbit or 32 KWord 3F0000h 3F7FFFh Top Boot Block Address lines A21-A0 512 Kbit or 32 KWord 2F8000h 2FFFFFh Total of 96 Main Blocks 512 Kbit or 32 KWord 300000h 307FFFh 64 Kbit or 4 KWord 3FF000h 3FFFFFh 64 Kbit or 4 KWord 3F8000h 3F8FFFh Total of 31 Main Blocks Total of 8 Parameter Blocks Bank B Bank A 64 Kbit or 4 KWord 000000h 000FFFh 512 Kbit or 32 KWord 0F8000h 0FFFFFh Bottom Boot Block Address lines A21-A0 64 Kbit or 4 KWord 007000h 007FFFh Total of 8 Parameter Blocks 512 Kbit or 32 KWord 008000h 00FFFFh 512 Kbit or 32 KWord 3F8000h 3FFFFFh 512 Kbit or 32 KWord 100000h 107FFFh Total of 31 Main Blocks Total of 96 Main Blocks Bank B Bank A |
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