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M68AR512DN70ZB1T Datasheet(PDF) 8 Page - STMicroelectronics |
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M68AR512DN70ZB1T Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 19 page M68AR512D 8/19 OPERATION The M68AR512D has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High) or Chip Select is asserted (E2 = Low), or UB/LB are de-asserted (UB/LB = High). An Output En- able (G) signal provides a high speed tri-state con- trol, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, LB and UB as summarized in the Operating Modes ta- ble (see Table 6). Table 6. Operating Modes Note: X = VIH or VIL. Read Mode The M68AR512D, when Chip Select (E2) is High, is in the read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip En- able (E1) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 8,388,608 locations in the static memory array, specified by the 19 ad- dress inputs. Valid data will be available at the eight or sixteen output pins within tAVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or tBLQV) rather than the address. Data out may be indeter- minate at tELQX, tGLQX and tBLQX, but data lines will always be valid at tAVQV. Figure 7. Address Controlled, Read Mode AC Waveforms Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low. Operation E1 E2 W G LB UB DQ0-DQ7 DQ8-DQ15 Power Deselected/Power-down VIH XXXXX Hi-Z Hi-Z Standby (ISB) Deselected/Power-down X VIL XXXX Hi-Z Hi-Z Standby (ISB) Deselected/Power-down XXXX VIH VIH Hi-Z Hi-Z Standby (ISB) Lower Byte Read VIL VIH VIH VIL VIL VIH Data Output Hi-Z Active (ICC) Lower Byte Write VIL VIH VIL X VIL VIH Data Input Hi-Z Active (ICC) Output Disabled VIL VIH X VIH X X Hi-Z Hi-Z Active (ICC) Upper Byte Read VIL VIH VIH VIL VIH VIL Hi-Z Data Output Active (ICC) Upper Byte Write VIL VIH VIL X VIH VIL Hi-Z Data Input Active (ICC) Word Read VIL VIH VIH VIL VIL VIL Data Output Data Output Active (ICC) Word Write VIL VIH VIL X VIL VIL Data Input Data Input Active (ICC) AI03961 tAVAV tAVQV tAXQX A0-A18 DQ0-DQ7 and/or DQ8-DQ15 VALID DATA VALID |
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