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M59MR032C120GC6T Datasheet(PDF) 8 Page - STMicroelectronics |
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M59MR032C120GC6T Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 49 page M59MR032C, M59MR032D 8/49 SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0- ADQ15). When Chip Enable E is at VIL and Out- put Enable G is at VIH the multiplexed address/ data bus is used to input addresses for the memo- ry array, data to be programmed in the memory ar- ray or commands to be written to the C.I. The address inputs for the memory array are latched on the rising edge of Latch Enable L. The address latch is transparent when L is at VIL. Both input data and commands are latched on the rising edge of Write Enable W. When Chip Enable E and Out- put Enable G are at VIL the address/data bus out- puts data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection status the Configuration Register status or the Status Register Data Polling bit ADQ7, the Toggle Bits ADQ6 and ADQ2, the Error bit ADQ5. The address/data bus is high imped- ance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL. Address Inputs (A16-A20). The five MSB ad- dresses of the memory array are latched on the rising edge of Latch Enable L. Chip Enable (E). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memo- ry array, while W remains at VIL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read op- eration. When G is at VIH the outputs are High im- pedance. Write Enable (W). This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W. Write Protect (WP). This input gives an addition- al hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description. Reset/Power-down Input (RP). The RP input provides hardware reset of the memory, and/or Power-down functions, depending on the Configu- ration Register status. Reset/Power-down of the memory is achieved by pulling RP to VIL for at least tPLPH. When the reset pulse is given, if the memory is in Read, Erase Suspend Read or Standby, it will output new valid data in tPHQ7V1 af- ter the rising edge of RP. If the memory is in Erase or Program modes, the operation will be aborted and the reset recovery will take a maximum of tPLQ7V. The memory will recover from Power- down (when enabled) in tPHQ7V2 after the rising edge of RP. Exit from Reset/Power-down changes the contents of the configuration register bits 14 and 15, setting the memory in asynchronous page mode read and power save function disabled. All blocks are protected and unlocked after a Reset/ Power-down. See Tables 29, 31 and Figure 14. Latch Enable (L). L latches the address bits ADQ0-ADQ15 and A16-A20 on its rising edge. The address latch is transparent when L is at VIL and it is inhibited when L is at VIH. Clock (K). The clock input synchronizes the memory to the microcontroller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration set- tings) when L is at VIL. K is don’t care during asyn- chronous page mode read and in write operations. Wait (WAIT). WAIT is an output signal used dur- ing burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E or G are high or RP is at VIL, and can be configured to be active during the wait cycle or one clock cy- cle in advance. |
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