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M7020R-083ZA1T Datasheet(PDF) 11 Page - STMicroelectronics |
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M7020R-083ZA1T Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 150 page  11/150 M7020R Figure 4. M7020R Block Diagram AI04271 Comparand Registers[15:0] Global Mask Registers [7:0] Information and Command Register Burst Read Register Burst Write Register Next Free Address Register Search Successful Index Registers [7:0] (All registers are 68-bit-wide) TAP Controller Pipeline and SRAM Control Arbitration Logic Command Decode and PIO Access PHS_L CLK2X RST_L DQ [67:0] CMD [8:0] CMDV ACK EOT Cmd Compare/PIO Data Configurable as 64K x 34 32K x 68 16K x 136 8K x 272 Data Array Configurable as 64K x 34 32K x 68 16K x 136 8K x 272 Mask Array Full Logic FULL [6:0] FULL FULO [1:0] ID [4:0] LHI [6:0] BHI [2:0] SSF SSV LHO [1:0] BHO [2:0] TAP SADR [21:0] OE_L WE_L CE_L ALE_L |
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