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V29C51002B-55T Datasheet(PDF) 9 Page - Mosel Vitelic, Corp |
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V29C51002B-55T Datasheet(HTML) 9 Page - Mosel Vitelic, Corp |
9 / 16 page 9 V29C51002T/V29C51002B Rev. 2.1 October 2000 MOSEL VITELIC V29C51002T/V29C51002B Functional Description The V29C51002T/V29C51002B consists of 512 equally-sized sectors of 512 bytes each. The 16 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The V29C51002 is available in two versions: the V29C51002T with the Boot Block address starting from 3C000H to 3FFFFH, and the V29C51002B with the Boot Block address starting from 00000H to 3FFFFH. Read Cycle A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1). Output Disable Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state. Standby The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state. Command Sequence The V29C51002T/V29C51002B does not provide the “reset” feature to return the chip to its normal state when an incomplete command sequence or an interruption has happened. In this case, normal operation (Read Mode) can be restored by issuing a “non-existent” command sequence, for example Address: 5555H, Data FFH. Byte Write Cycle The V29C51002T/V29C51002B is programmed on a byte-by-byte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2). During the byte write cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled. Sector Erase Cycle The V29C51002T/V29C51002B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, 16KB Boot Block 512 Byte 512 Byte 512 Byte 512 Byte 512 Byte 512 Byte 16KB Boot Block V29C51002T V29C51002B 3FFFFH 3C000H 00000H 03FFFH 51002-15 00000H 16KB Boot Block = 32 Sectors Table 1. Operation Modes Decoding NOTES: 1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max. 2. PD: The data at the byte address to be programmed. Decoding Mode CE OE WE A0 A1 A9 I/O Read VIL VIL VIH A0 A1 A9 READ Byte Write VIL VIH VIL A0 A1 A9 PD Standby VIH XXXXX HIGH-Z Autoselect Device ID VIL VIL VIH VIH VIL VH CODE Autoselect Manufacture ID VIL VIL VIH VIL VIL VH CODE Enabling Boot Block Protection Lock VIL VH VIL XX VH X Disabling Boot Block Protection Lock VH VH VIL XX VH X Output Disable VIL VIH VIH X X X HIGH-Z |
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