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TMS320F240PQS Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320F240PQS Datasheet(HTML) 9 Page - Texas Instruments |
9 / 105 page TMS320F240 DSP CONTROLLER SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION SUPPLY SIGNALS CVSS 8 I Digital core logic ground reference VSS 3 14 20 29 46 59 I Digital logic gro nd reference VSS 59 61 71 92 104 113 120 I Digital logic ground reference VSSA 87 I Analog ground reference DV 2 13 21 47 I Digital I/O logic supply voltage DVDD 47 62 93 103 121 I Digital I/O logic supply voltage CV 7 I Digital core logic s ppl oltage CVDD 60 I Digital core logic supply voltage VCCA 84 I Analog supply voltage VREFHI 85 I ADC analog voltage reference high VREFLO 86 I ADC analog voltage reference low TEST SIGNALS TCK 30 I JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction reg- ister, or selected test data register of the C2xx core on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI 31 I JTAG test data input (TDI). TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 34 O/Z JTAG test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state when OFF is active low. TMS 33 I JTAG test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. † I = input, O = output, Z = high impedance |
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