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M74HC181 Datasheet(PDF) 1 Page - STMicroelectronics |
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M74HC181 Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 13 page M74HC181 October 1993 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ORDER CODES : M74HC181M1R M74HC181B1R PIN CONNECTIONS (top view) B1R (Plastic Package) . HIGH SPEED tPD = 13 ns (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) at TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS181 M1R (Micro Package) The 74HC181 is a high speed CMOS ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR fabricated with silicon gate C 2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These circuits per- form 16 binary arithmetic operations on two 4-bit words as shown in tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made available in these devices for fast, simultaneous carry gener- ation by means of two cascade-outputs (pins 15 and 17) for the four bits in the package. When used in con- junction with the M54HC182 or M74HC182, full carry look-ahead circuits, high-speed arithmetic operations can be performed. These circuits will accomodate ac- tive-high or active-low data, if the pin designations are interpreted as shown below. Subtraction is accom- plished by 1,s complement addition where the 1’s complement of the subtrahend is generated internally. The resultant output is 1–B–1, which requires an end- around or forced carry to produce A–B. The 181 can also be utilized as a comparator. The A = B output is internally decoded from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high level to indicated equality (A = B). The ALU should be DESCRIPTION * Open drain Output Structure 1/13 |
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