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LM2507GR Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LM2507GR Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 22 page Recommended Input Timing Requirements (Continued) Note 5: Total Supply Current Conditions: CPU Mode, worse case data pattern, 19.2MHz CLK, DES CL = 15pF, TYP – VDDIO =VDDA =VDDcore = 1.8V, MAX – VDDIO = 3.0V and VDDA =VDDcore = 2.0V. Note 6: Applies to WR* and RD* outputs only.. Note 7: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality. Note 8: Guaranteed functionally by the IDDZ parameter. See also Figure 7. Note 9: This is a functional parameter and is guaranteed by design or characterization. Timing Diagrams Functional Description BUS OVERVIEW The LM2507 is a dual link MST/SLV configurable part that supports a 8, 9 or 16-bit CPU (i80 style) interface. The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termination is provided internal to the MPL receiver. A maximum raw throughput of 320 Mbps (raw) is possible with this chipset. When the protocol overhead is taken into account, a maximum data throughput of 240 Mbps is possible. The MPL interface is designed for use with common 50 Ω to 100Ω lines using standard materials and connectors. Lines may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 20cm. SERIAL BUS TIMING Data valid is relative to both edges for a CPU WRITE as shown in Figure 4. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps. 20186016 FIGURE 1. Serial Data Valid — SLV Input Set and Hold Time 20186018 FIGURE 2. SLV Output Rise and Fall Time 20186002 FIGURE 3. MPL Point-to-Point Bus www.national.com 6 |
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