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ADS7885 Datasheet(PDF) 7 Page - Burr-Brown (TI) |
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ADS7885 Datasheet(HTML) 7 Page - Burr-Brown (TI) |
7 / 22 page www.ti.com DEVICE INFORMATION 3 2 4 6 1 VDD GND VIN CS SCLK SDO 5 ADS7884 NORMAL OPERATION ADS7884 ADS7885 SLAS567 – MARCH 2008 TIMING REQUIREMENTS (see Figure 1) (continued) All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified. PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT Delay time, CS and 10th falling edge of clock to VDD = 3 V –2 4 td6 enter in powerdown (use max spec not to accidently ns VDD = 5 V –2 3 enter in powerdown) Figure 3 SOT23 PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. VDD 1 – Power supply input also acts like a reference voltage to ADC. GND 2 – Ground for power supply, all analog and digital signals are referred with respect to this pin. VIN 3 I Analog signal input SCLK 4 I Serial clock SDO 5 O Serial data out CS 6 I Chip select signal, active low The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 2 leading zeros, followed by 10-bit data in MSB first format and padded by 4 lagging zeros. The falling edge of CS clocks out the first zero, and a second zero is clocked out on FIRST falling edge of the clock. Data is in MSB first format with the MSB being clocked out on the 2nd falling edge. Data is padded with four lagging zeros as shown in Figure 1. The conversion ends on the first rising edge of SCLK after the 11th falling edge. At this point the device enters the acquisition phase. This point is indicated by b in Figure 1. Figure 1 shows device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any time after 11 clocks have elapsed. SDO goes to 3-state with the CS high level. The next conversion should not be started (by pulling CS low) until the end of the quiet sampling time (tq) after SDO goes to 3-state or until the minimum acquisition time (tacq) has elapsed. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle. (Also refer to the Powerdown Mode section for more details.) CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on powerup sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in the Specifications table. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS7884 ADS7885 |
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