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ADSP-21990BSTZ Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-21990BSTZ Datasheet(HTML) 3 Page - Analog Devices |
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3 / 50 page  ADSP-21990 Rev. A | Page 3 of 50 | August 2007 GENERAL DESCRIPTION The ADSP-21990 is a mixed-signal DSP controller based on the ADSP-2199x DSP core, suitable for a variety of high perfor- mance industrial motor control and signal processing applications that require the combination of a high performance DSP and the mixed-signal integration of embedded control peripherals such as analog-to-digital conversion. Target appli- cations include: industrial motor drives, uninterruptible power supplies, optical networking control, data acquisition systems, test and measurement systems, and portable instrumentation. The ADSP-21990 integrates the fixed-point ADSP-2199x fam- ily-based architecture with a serial port, an SPI-compatible port, a DMA controller, three programmable timers, general-purpose programmable flag pins, extensive interrupt capabilities, on- chip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment. The ADSP-21990 architecture is code compatible with previous ADSP-217xx based ADMCxxx products. Although the architec- tures are compatible, the ADSP-21990, with ADSP-2199x architecture, has a number of enhancements over earlier archi- tectures. The enhancements to computational units, data address generators, and program sequencer make the ADSP-21990 more flexible and easier to program than the pre- vious ADSP-21xx embedded DSPs. Indirect addressing options provide addressing flexibility—pre- modify with no update, pre- and post-modify by an immediate 8-bit, twos complement value and base address registers for eas- ier implementation of circular buffering. The ADSP-21990 integrates 8K words of on-chip memory con- figured as 4K words (24-bit) of program RAM, and 4K words (16-bit) of data RAM. Fabricated in a high speed, low power, CMOS process, the ADSP-21990 operates with a 6.25 ns instruction cycle time for a 160 MHz CCLK and with a 6.67 ns instruction cycle time for a 150 MHz CCLK. The flexible architecture and comprehensive instruction set of the ADSP-21990 support multiple operations in parallel. For example, in one processor cycle, the ADSP-21990 can: • Generate an address for the next instruction fetch. • Fetch the next instruction. • Perform one or two data moves. • Update one or two data address pointers. • Perform a computational operation. These operations take place while the processor continues to: • Receive and transmit data through the serial port. • Receive or transmit data over the SPI port. • Access external memory through the external memory interface. • Decrement the timers. • Operate the embedded control peripherals (ADC, PWM, EIU, etc.). DSP CORE ARCHITECTURE • 6.25 ns instruction cycle time (internal), for up to 160 MIPS sustained performance (6.67 ns instruction cycle time for 150 MIPS sustained performance). • ADSP-218x family code compatible with the same easy to use algebraic syntax. • Single cycle instruction execution. • Up to 1M words of addressable memory space with 24 bits of addressing width. • Dual-purpose program memory for both instruction and data storage. • Fully transparent instruction cache allows dual operand fetches in every instruction cycle. • Unified memory space permits flexible address generation, using two independent DAG units. • Independent ALU, multiplier/accumulator, and barrel shifter computational units with dual 40-bit accumulators. • Single cycle context switch between two sets of computa- tional and DAG registers. • Parallel execution of computation and memory instructions. • Pipelined architecture supports efficient code execution at speeds up to 160 MIPS. • Register file computations with all nonconditional, non- parallel computational instructions. • Powerful program sequencer provides zero overhead loop- ing and conditional instruction execution. • Architectural enhancements for compiled C code efficiency. • Architecture enhancements beyond ADSP-218xx family are supported with instruction set extensions for added registers, ports, and peripherals. The clock generator module of the ADSP-21990 includes clock control logic that allows the user to select and change the main clock frequency. The module generates two output clocks: the DSP core clock, CCLK; and the peripheral clock, HCLK. CCLK can sustain clock values of up to 160 MHz, while HCLK can be equal to CCLK or CCLK/2 for values up to a maximum 80 MHz peripheral clock at the 160 MHz CCLK rate. The ADSP-21990 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single word instruction can be executed in a single processor cycle. The ADSP-21990 assembly language uses an algebraic syntax for ease of coding and readability. A com- prehensive set of development tools supports program development. |
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