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MK5027PLCC52 Datasheet(PDF) 2 Page - STMicroelectronics |
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MK5027PLCC52 Datasheet(HTML) 2 Page - STMicroelectronics |
2 / 19 page Table 1: Pin Description. LEGEND: I Input only O Output only IO Input/Output 3S 3-State OD Open Drain (no internal pull-up) Signal Name Pin(s) Type Descriplion DAL<15:00> 2-9 40-47 IO/3S The time multiplexed Data Address bus. During the address portion of a memory transfer, DALe15:00 contains the lower 16 bits of the memory address. During the data portion of a memory transfer, DAL<15:00> contains the read or write data, depending on the type of transfer. READ 10 IO/3S READ indicates the type of operation that the bus controller is performing during a bus transaction. READ is driven by the MK5027 only while it is the BUS MASTER. READ is valid during the entire bus transaction and is tristated at all other times. MK5027 as a Bus Slave: READ = HIGH - Data is placed on the DAL lines by the chip. READ = LOW - Data is taken off the DAL lines by the chip. MK5027 as a Bus Master: READ = HIGH - Data is taken off the DAL lines by the chip. READ = LOW - Data is placed on the DAL lines by the chip. INTR 11 O/OD INTERRUPT is an attention interrupt line that indicates that one or more of the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT. INTERRUPT is enabled by CSR0<0.9>, INEA = 1. DALI 12 O/3S DAL IN is an external bus transceiver control line. DALI is driven by the MK5027 only while it is the BUS MASTER. DALI is asserted by the MK5027 when | ads from the DAL lines during the data portion of a READ transfer. DALI is not asserted during a WRITE transfer. DALO 13 O/3S DAL OUT is an external bus transceiver control line. DALO is driven by the MK5027 only while it is the BUS MASTER. DALO is asserted by the MK5027 when it drives the DAL lines during the address portion of a READ transfer or for the duration of a WRITE transfer. DAS 14 IO/3S DATA STROBE defines the data portio,n of a transaction. By definition, data is stable and valid at the low to high transition of DAS. This signal is driven by the MK5027 while it is the BUS MASTER. During the BUS SLAVE operation, this pin is used as an input. At all other times the signal is tristated. BMO BYTE BUSREL 15 IO/3S I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set to a one, pin 15 becomes input BUSREL and is used by the host to signal the MK5027 to terminate a DMA burst after the current bus transfer has completed. If bit 06 is clear the pin 15 is an output and behaves as described below for pin 16. Note: Pin out shown is for 48 pin dip. MK5027 2/19 |
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