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MK50H28Q25 Datasheet(PDF) 10 Page - STMicroelectronics |
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MK50H28Q25 Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 64 page  3.1.7 DMA Controller The MK50H28 has an on-chip DMA Controller cir- cuit. This allows it to access memory without re- quiring host software intervention. Whenever the MK50H28 requires access to the host memory it will negotiate for mastership of the bus. Upon gaining control of the bus the MK50H28 will begin transferring data to or from memory. The MK50H28 will perform memory transfers until either it has nothing more to transfer, it has reached its DMA burst limit (user programmable), or the BUSREL pin is driven low. In any case, it will complete the current bus transfer before re- leasing bus mastership back to the host. If during a memory transfer, the memory does not respond within 256 SCLK cycles, the MK50H28 will re- lease ownership of the bus immediately and the MERR bit will be set in CSR0. The DMA burst limit can be programmed by the user through CSR4. In 16 bit mode the limit can be set to 1 word, 8 words, or unlimited word transfers. In 8 bit mode,it can be set to 2 bytes, 16 bytes, or un- limited byte transfers. For high speed data lines (i.e. > 1 Mbps) a burst limit of 8 words, 16 bytes or unlimited is suggested to allow maximum throughput. The byte ordering of the DMA transfers can be programmed to account for differences in proces- sor architectures or host programming languages. Byte ordering can be programmed separately for data and control information. Data information is defined as all contents of data buffers; control in- formation is defined as anything else in the shared memory space (i.e. initialization block, de- scriptors, etc). For more information see section 4.1.2.5 on Control and Status Register 4. 3.1.8 Bus Slave Circuitry The MK50H28 contains a bank of internal con- trol/status registers (CSR0-5) which can be ac- cessed by the host as a peripheral. The host can read or write to these registers like any other bus slave. The contents of these registers are listed in Section 4 and bus signal timing is described in Figures 13 and 14. 3.2 Memory/Buffer Management Overview The MK50H28 memory structure (Fig. 3) consists of various blocks of off-chip memory. Only the Control/Status registers, some RAM and firmware ROM are onboard the chip. The Initialization Block, Priority DLCI Block, Status Buffer, Address Lookup Table (ALT), Context Table (CT), Trans- mit/Receive Rings and Buffers are in the off-chip memory. The buffer management is a circular queue of tasks in memory called descriptor rings. There are separate rings to describe the transmit and receive operations. The MK50H28 buffer man- agement mechanism will handle data frames which are longer than the length of an individual buffer. This is done by a chaining method which utilizes multiple buffers. The MK50H28 tests the next segment in the descriptor ring in a look- ahead manner. If the packet is too long for one buffer, the next buffer will be used after filling the first buffer (that is chained to the previous buffer). The MK50H28 will then look ahead to the next buffer, and chain that buffer also if necessary, and so on. 3.2.1 Initialization Block The MK50H28 initialization information is located in a block of off- chip memory called the Initializa- tion Block. The Initialization Block consists of 44 contiguous words of memory starting on a word boundary. The starting address for the initializa- tion block, IADR, is defined in the CSR2 and CSR3 registers inside the MK50H28. This mem- ory is assembled by the HOST, and the first 15 words are accessed by the MK50H28 during in- itialization. The Initialization Block (refer to sec- tion 4.2) is comprised of: A. Mode of Operation. B. The nN1, nN2, and nN3 counters. C. The dN1(Max Frame Length) counter. D. The nT1, nT2 and TP (Transmit Polling) timers. E. Pointer to the beginning of Context Table. F. Pointer to the beginning of Address LookupTable. G. Pointer to the beginning of Status Buffer. H. Error Counters and Statistics. 3.2.1.1 Priority DLCI Block (PDB) The Priority DLCI Block consists of Context Table indices for the priority channels. These indices are a mechanism through which the host can de- mand the MK50H28 to immediately service cer- tain desired DLCIs. The host should first set up entries in the PDB before setting the PTDMD bit in CSR2. In response to that, the MK50H28, after completing transmission service of its current DLCI, will jump to the PDB rather than advancing to the next entry in the context table. After servic- ing all active entries in the PDB, the MK50H28 will return to the Context Table and resume the transmission service that was in progress before it was interrupted. 3.2.1.2 Interrupt Descriptor Rings The MK50H28 has two descriptor ring structures for the purpose of queing Transmit and Receive interrupts. The pointers to these two descriptor rings are located at IADR+24 thru IADR+30 in the initialization Block. These descriptor rings are of MK50H28 10/64 |
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