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ICS858012AK Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS858012AK Datasheet(HTML) 9 Page - Integrated Circuit Systems |
9 / 15 page 858012AK www.icst.com/products/hiperclocks.html REV. A NOVEMBER 28, 2005 9 Integrated Circuit Systems, Inc. ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO- 2.5V, 3.3V LVPECL FANOUT BUFFER PRELIMINARY The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR 3.3V LVPECL OUTPUTS V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN FIGURE 5B. LVPECL OUTPUT TERMINATION FIGURE 5A. LVPECL OUTPUT TERMINATION OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. RECOMMENDATIONS FOR UNUSED OUTPUT PINS |
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