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TSB12LV31 Datasheet(PDF) 10 Page - Texas Instruments |
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TSB12LV31 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 38 page  TSB21LV03 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SLLS230A – MARCH 1996 – REVISED DECEMBER 1996 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 device PARAMETER TEST CONDITION MIN TYP MAX UNIT VDD = 3.3 V Node transmitting or repeating 114 mA IDD Supply current DD Node receiving 140 mA DD y VDD = 3.6 V 175 mA VDD = 3.6 V, Power-down mode 10 mA VIT Power status input threshold voltage (CPS) RL = 400 kΩ 4.7 7.5 V VOH High-level output voltage VDD = min, IOH max VDD–0.55 V VOL Low-level output voltage VDD = max, IOL min 0.5 V II Input current (LREQ, LPS, PD, TESTM1, TESTM2, PC0, PC1, PC2) VI = VDD or 0 ±1 µA Ioff Off-state output current (CTL0, CTL1, D0, D1, D2, D3, C/LKON) VO = VDD or 0 ±5 µA Pullup current (RESET) VI = 1.5 V –20 –40 –80 µA Pullup current (RESET) VI = 0 –22 –45 –90 µA Power-up reset time (RESET) 2 ms VTH+ Positive arbitration comparator-input threshold voltage 89 168 mV VTH– Negative arbitration comparator- input threshold voltage –168 –89 mV VIT Speed-signal input threshold volt- age 49 131 mV VIT+ Positive input threshold voltage (LREQ, CTLn, Dn) VDD/2+0.12 VDD/2+0.66 V VIT– Negative input threshold voltage (LREQ, CTLn, Dn) VDD/2–0.66 VDD/2–0.12 V VO Output voltage (TPBIAS1, TPBIAS2, TPBIAS3 termianls) 1.665 2.015 V Bus holding current (LREQ, CTLn, Dn termianls) VI = 1/2 (VDD) 250 µA thermal characteristics PARAMETER TEST CONDITION MIN TYP MAX UNIT R θJA Junction-to-free-air thermal resistance Board mounted, No air flow 92.5 _C/W R θJC Junction-to-case thermal resistance 10.4 _C/W switching characteristics PARAMETER MEASURED TEST CONDITION MIN TYP MAX UNIT Jitter, transmit TPA, TPB ±0.25 ns Skew rate, transmit Between TPA and TPB ±0.15 ns tr Rise time, transmit 10% to 90% RL=56Ω, CL=10 pF 2.2 ns tf Fall time, transmit 90% to 10% RL=56Ω, CL=10 pF 2.2 ns tsu Setup time, Dn, CTLn, LREQ ↑↓ to SYSCLK ↑ 50% to 50% See Figure 1 5 ns th Hold time, Dn, CTLn, LREQ ↑↓ before SYSCLK ↑ 50% to 50% See Figure 1 2 ns td Delay time, SYSCLK ↑ to Dn, CTLn↑↓ 50% to 50% See Figure 2 2 11 ns |
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