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A6285EET-T Datasheet(PDF) 6 Page - Allegro MicroSystems |
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A6285EET-T Datasheet(HTML) 6 Page - Allegro MicroSystems |
6 / 13 page 16-Channel Constant-Current Latched LED Driver with Open LED Detection and Dot Correction A6285 6 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com SWITCHING CHARACTERISTICS at TA1 = 25°C, VDD = VIH = 3.0 to 5.5 V, VDS = 1 V, VIL = 0 V, REXT = 1.2 kΩ, IO = 40 mA, VL = 3 V, RL = 51 Ω, CL = 15 pF (see table 9) Characteristic Symbol Test Conditions Min. Typ.2 Max. Unit Clock Frequency fCLK CLK – – 30 MHz Clock Pulse Duration twh0/twl0 CLK = High/Low 16 – – ns Clock Frequency (cascaded) fCLKC CLK – – 25 MHz LE Pulse Duration twh1 LE = High 20 – – ns Setup Time tsu0 SDI to CLK↑ 10 – – ns tsu1 CLK↑ to LE↑ 10 – – ns tsu2 MODE↑↓ to CLK↑ 10 – – ns tsu3 MODE↑↓ to LE↑ 10 – – ns Hold Time th0 CLK↑ to SDI 10 – – ns th1 LE↓ to CLK↑ 10 – – ns th2 CLK↑ to MODE↑↓ 10 – – ns th3 LE↓ to MODE↑↓ 10 – – ns Rise Time tr0 SDO, 10/90% points (see figure 1) – – 16 ns tr1 OUTx, VDD = 5 V, DC = 127, 10/90% points (see figure 2) –10 30 ns Fall Time tf0 SDO, 10/90% points (see figure 1) – – 16 ns tf1 OUTx, VDD = 5 V, DC = 127, 10/90% points (see figure 2) –10 30 ns Propagation Delay Time tpd0 CLK↑ to SDO↑↓ (see figure 1) – – 30 ns tpd1 MODE↑↓ to SDO↑↓ (see figure 1) – – 30 ns tpd2 O¯¯E¯↓ to OUT0↑↓ (see figure 2) – – 60 ns tpd3 LE↑ to OUT0↑↓ (see figure 2) – – 60 ns tpd4 OUTx↑↓ to FAULT↑↓ (see figures 2 and 3) – – 1000 ns tpd5 LE↑ to IOUT (DC) (see figure 2) – – 200 ns LOD Sample and Read Time tLOD LE1↑ to LE2↑ 1660 – – ns Output Delay Time td OUTx↑↓ to OUT(x+1)↑↓ (see figure 2) 10 20 40 ns 1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits d maximum and minimum limits. SDO 15 pF OUTx A6285 51 15 pF A6285 FAULT A6285 1.2 k Parameter Measurement Information Figure 1. Test circuit for tr0, tf0, td0, and td1 Figure 2. Test circuit for tr1, tf1, tpd2, tpd3, tpd5, and tpd6 Figure 3. Test circuit for tpd4 |
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