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EM620FV8BS Series
Low Power, 256Kx8 SRAM
6
tRC
Address
CS1
CS2
OE
Data Out
tCO1,2
tOH
tOE
High-Z
tOHZ
tWHZ
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
Data Valid
tOLZ
tLZ1,2
tAA
tHZ1,2
tRC
Address
tAA
Data Valid
tOH
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
Data Out
TIMING DIAGRAMS
NOTES (READ CYCLE)
1. tHZ 1,2and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to
device interconnection.