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SN74LVTH18502APMG4 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVTH18502APMG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 40 page SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A 3.3V ABT SCAN TEST DEVICES WITH 18BIT UNIVERSAL BUS TRANSCEIVERS SCBS668C − JULY 1996 − REVISED JUNE 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Members of the Texas Instruments SCOPE Family of Testability Products D Members of the Texas Instruments Widebus Family D State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) D Support Unregulated Battery Operation Down to 2.7 V D UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode D Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors D B-Port Outputs of ’LVTH182502A Devices Have Equivalent 25- Ω Series Resistors, So No External Resistors Are Required D Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture D SCOPE Instruction Set − IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ − Parallel-Signature Analysis at Inputs − Pseudorandom Pattern Generation From Outputs − Sample Inputs/Toggle Outputs − Binary Count From Outputs − Device Identification − Even-Parity Opcodes D Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings description The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Copyright 2004, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. SCOPE, Widebus, and UBT are trademarks of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. |
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