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M95020-BN3P Datasheet(PDF) 10 Page - STMicroelectronics |
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M95020-BN3P Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 37 page M95040, M95020, M95010 10/37 Status Register Figure 7. shows the position of the Status Register in the control logic of the device. This register con- tains a number of control bits and status bits, as shown in Table 3.. Bits b7, b6, b5 and b4 are always read as 1. WIP bit. The Write In Progress bit is a volatile read-only bit that is automatically set and reset by the internal logic of the device. When set to a 1, it indicates that the memory is busy with a Write cy- cle. WEL bit. The Write Enable Latch bit is a volatile read-only bit that is set and reset by specific in- structions. When reset to 0, no WRITE or WRSR instructions are accepted by the device. BP1, BP0 bits. The Block Protect bits are non- volatile read-write bits. These bits define the area of memory that is protected against the execution of Write cycles, as summarized in Table 4.. Table 3. Status Register Format Data Protection and Protocol Control To help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. The main security measures can be summarized as follows: – The WEL bit is reset at power-up. – Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile Write cycle (in the memory array or in the Status Register). – Accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. – Invalid Chip Select (S) and Hold (HOLD) transitions are ignored. For any instruction to be accepted and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the next rising edge of Serial Clock (C). For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (ex- cept in the case of RDSR and READ instructions). Moreover, the "next rising edge of CLOCK" might (or might not) be the next bus transaction for some other device on the bus. When a Write cycle is in progress, the device pro- tects it against external interruption by ignoring any subsequent READ, WRITE or WRSR instruc- tion until the present cycle is complete. Table 4. Write-Protected Block Size b7 b0 1 1 1 1 BP1 BP0 WEL WIP Block Protect Bits Write Enable Latch Bit Write In Progress Bit Status Register Bits Protected Block Array Addresses Protected BP1 BP0 M95040 M95020 M95010 0 0 none none none none 0 1 Upper quarter 180h - 1FFh C0h - FFh 60h - 7Fh 1 0 Upper half 100h - 1FFh 80h - FFh 40h - 7Fh 1 1 Whole memory 000h - 1FFh 00h - FFh 00h - 7Fh |
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