W39L020

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Algorithm. Upon executing the algorithm, the system is not required to provide further controls or

timings. The device will automatically provide adequate internally generated program pulses and verify

the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 (also used as Data

Polling) is equivalent to the data written to this bit at which time the device returns to the read mode

and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device

requires that a valid address to the device be supplied by the system at this particular instance of time

for Data Polling operations. Data Polling must be performed at the memory location which is being

programmed.

Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a

hardware reset occurs during the programming operation, the data at that particular location will be

corrupted.

Programming is allowed in any sequence and across sector boundaries. Beware that a data "0"

cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop

toggling. Only erase operations can convert "0"s to "1"s.

Refer to the Programming Command Flow Chart using typical command strings and bus operations.

Chip Erase Command

Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the

"set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase

command.

Chip erase does not require the user to program the device prior to erase. Upon executing the

Embedded Erase Algorithm command sequence the device will automatically erase and verify the

entire memory for an all one data pattern. The erase is performed sequentially on each sectors at the

same time (see "Feature"). The system is not required to provide any controls or timings during these

operations.

The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and

terminates when the data on DQ7 is "1" at which time the device returns to read the mode.

Refer to the Erase Command Flow Chart using typical command strings and bus operations.

Sector/Page Erase Command

Sector/page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by

writing the "set-up" command. Two more "unlock" write cycles then follows by the sector erase

command. The sector/page address (any address location within the desired sector/page) is latched

on the falling edge of #WE, while the command (30H/50H) is latched on the rising edge of #WE.

Sector/page erase does not require the user to program the device prior to erase. When erasing a

sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is

not required to provide any controls or timings during these operations.

The automatic sector/page erase begins after the erase command is completed, right from the rising

edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data

on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be

performed at an address within any of the sectors/pages being erased.

Refer to the Erase Command flow Chart using typical command strings and bus operations.