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ISPLSI3192-100LB272I Datasheet(PDF) 3 Page - Lattice Semiconductor |
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ISPLSI3192-100LB272I Datasheet(HTML) 3 Page - Lattice Semiconductor |
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3 / 15 page  Specifications ispLSI 3192 3 Description (Continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 192 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. The 192 I/O Cells are grouped into six sets of 32 bits. Each of these I/O groups is associated with a logic Megablock through the use of the ORP. Each Megablock is able to provide one Product Term Output Enable (PTOE) signal which is globally distributed to all I/O cells. That PTOE signal can be generated within any GLB in the Megablock. Each I/O cell can select either a Global OE or a PTOE. Four Twin GLBs, 32 I/O Cells and two ORPs are con- nected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The outputs of the four Twin GLBs are connected to a set of 32 I/O cells by the two ORPs. The ispLSI 3192 device contains six of these Megablocks. The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equal- ized to minimize timing skew and logic glitching. Clocks in the ispLSI 3192 device are provided through five dedicated clock pins. The five pins provide three clocks to the Twin GLBs and two clocks to the I/O cells. The table below lists key attributes of the device along with the number of resources available. An additional feature of the ispLSI 3192 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device's input and output pins. All I/O pins have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one. The ispLSI 3192 supports all IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST and SAMPLE. Key Attributes of the ispLSI 3192 e t u b i r t t Ay t i t n a u Q s B L G n i w T 4 2 s r e t s i g e R 4 8 3 s n i P O / I 2 9 1 s k c o l C l a b o l G 5 E O l a b o l G 2 E O t s e T 1 2 9 1 3 / 3 0 0 - e l b a T |
Similar Part No. - ISPLSI3192-100LB272I |
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Similar Description - ISPLSI3192-100LB272I |
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