Electronic Components Datasheet Search |
|
ZPSD503B1-C-70U Datasheet(PDF) 6 Page - STMicroelectronics |
|
ZPSD503B1-C-70U Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 153 page PSD5XX Family 3 2.0 Key Features Introduction (cont.) The Power Management Unit (PMU) of the PSD5XX enables the user to control the power consumption on selected functional blocks, based on system requirements. For microcontrollers that do not generate a chip select input for the PSD, the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down or Sleep Mode, based on the inactivity of ALE (or AS). Implementing your design has never been easier than with PSDsoft—WSI’s software development suite. Using PSDsoft, you can do the following: • Configure your PSD5XX to work with virtually any microcontroller • Specify what you want implemented in the programmable logic using a design file • Simulate your design • Download your design to the part using a programmer. t Single-chip programmable peripheral for microcontroller-based applications t 256K to 1 Mbit of UV EPROM with the following features: • Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16 • Divided into four equally-sized mappable blocks for optimized address mapping • As fast as 70 ns access time, which includes address decoding • Built-in Zero-power technology t 16 Kbits SRAM is configurable as 2K x 8 or 1K x 16. The access time can be as quick as 70 ns, including address decoding. The contents of the SRAM can be battery-backed by connecting a battery to the Vstby pin. The SRAM was also designed using Zero-power technology t 40 I/O pins (divided into five 8-bit ports) that can be individually configured for: • Standard MCU I/O • PLD/macrocell I/O • Latched address output • High-order address inputs • Special function I/O • Open-drain output t Three Zero-power Programmable Logic Devices (ZPLDs): the Decode PLD (DPLD), the General-purpose PLD (GPLD), and the Peripheral PLD (PPLD) can be used for: • Up to 61 input and 140 output product terms • 24 Macrocells and I/O • Decode up to 16 MB of address • State machines and state logic • Generate external signals (chip selects, bus interface, etc.) t Microcontroller logic that eliminates the need for external “glue logic” has the following features: • Ability to interface to multiplexed and non-multiplexed buses • Built-in address latches for multiplexed address/data bus • ALE and Reset polarity are programmable • Multiple configurations are possible for interface to many different microcontrollers t Four 16-bit Counter/Timers that have five modes of operation and can be controlled by the PPLD macrocells. Modes of operation are: pulse and waveform generation, time capture, event counting, and a watchdog timer (real time clock). t Eight input priority encoded Interrupt Controller. Four interrupts are generated by the PPLD and are user defined. The other four interrupts are generated by the Counter/Timer’s terminal count flags. Each interrupt can be individually masked and configured as edge or level sensitive. t Page logic is connected to the ZPLDs and expands the MCU address space to up to 16 times |
Similar Part No. - ZPSD503B1-C-70U |
|
Similar Description - ZPSD503B1-C-70U |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |